Three-dimensional memory devices containing memory stack structures with position-independent threshold voltage

ABSTRACT

The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region by forming a doped pocket region. The doped pocket region has the same conductivity type as a doped well that constitutes horizontal portions of the semiconductor channels that extend into the memory stack structures, and has a higher dopant concentration level than the doped well. The doped pocket region and a source region can be simultaneously formed by implanting p-type dopants and n-type dopants into a surface portion of the substrate underlying a backside contact trench. By selecting dopant species having different diffusion rates, the doped pocket region can surround the source region. The process parameters of the anneal process can be selected such that the interface between the dopant pocket region and the doped well underlies outermost memory stack structures.

FIELD

The present disclosure relates generally to the field of semiconductordevices and specifically to three-dimensional semiconductor devices,such as vertical NAND strings, and methods of making thereof.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell aredisclosed in an article by T. Endoh, et. al., titled “Novel Ultra HighDensity Memory With A Stacked-Surrounding Gate Transistor (S-SGT)Structured Cell”, IEDM Proc. (2001) 33-36.

SUMMARY

According to an aspect of the present disclosure, a monolithicthree-dimensional memory device comprises a stack of alternating layerscomprising insulating layers and electrically conductive layers andlocated over a semiconductor region having a doping of a firstconductivity type at a first dopant concentration level, a plurality ofmemory stack structures extending through the stack, a first backsidecontact via structure extending through the stack and laterally spacedfrom the plurality of memory stack structures, a source regionunderlying the first backside contact via structure and having a dopingof a second conductivity that is the opposite of the first conductivitytype, and a doped pocket region laterally surrounding the source region,having a doping of the first conductivity type at a second dopantconcentration level that is higher than the first dopant concentrationlevel. An interface between the doped pocket region and thesemiconductor region underlies at least one first memory stack structureamong the plurality of memory stack structures.

According to another aspect of the present disclosure, a method ofmanufacturing a memory device is provided. A stack of alternating layerscomprising insulating layers and spacer material layers is formed over asubstrate. A plurality of memory stack structures is formed through thestack. A backside contact trench extending through the stack and to thesubstrate is formed. An implanted region is formed in a portion of thesubstrate underlying the backside contact trench by implanting first andsecond conductivity type through the backside contact trench. The firstand second conductivity type dopants are simultaneously outdiffusedemploying an anneal process performed at an elevated temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a vertical cross-sectional view of an exemplary structureafter formation of a stack including an alternating plurality ofmaterial layers and memory openings extending through the stackaccording to an embodiment of the present disclosure.

FIGS. 2A-2H are sequential vertical cross-sectional views of a memoryopening within the exemplary structure during various processing stepsemployed to form a memory stack structure according to an embodiment ofthe present disclosure.

FIG. 3 is a vertical cross-sectional view of the exemplary structureafter formation of memory stack structures according to an embodiment ofthe present disclosure.

FIG. 4 is a vertical cross-sectional view of the exemplary structureafter formation of a stepped terrace and a retro-stepped dielectricmaterial portion according to an embodiment of the present disclosure.

FIG. 5A is a vertical cross-sectional view of the exemplary structureafter formation of a backside contact trench and an implanted regionaccording to an embodiment of the present disclosure.

FIG. 5B is a partial see-through top-down view of the exemplarystructure of FIG. 5A. The vertical plane A-A′ is the plane of thevertical cross-sectional view of FIG. 5A.

FIG. 6A is a vertical cross-sectional view of the exemplary structureafter formation of a source region and a doped pocket region accordingto an embodiment of the present disclosure.

FIG. 6B is a horizontal cross-sectional view of exemplary structure ofFIG. 6A along the horizontal plane B-B′ of FIG. 6A.

FIG. 6C is a vertical cross-sectional view of the exemplary structure ofFIG. 6B along the vertical plane C-C′ of FIG. 6B.

FIG. 6D is a vertical cross-sectional view of the exemplary structure ofFIG. 6B along the vertical plane D-D′ of FIG. 6B.

FIG. 7 is a vertical cross-sectional view of the exemplary structureafter formation of backside recesses according to an embodiment of thepresent disclosure.

FIG. 8 is a vertical cross-sectional view of the exemplary structureafter formation of electrically conductive layers according to anembodiment of the present disclosure.

FIG. 9 is a vertical cross-sectional view of the exemplary structureafter removal of a deposited conductive material from within thebackside contact trench according to an embodiment of the presentdisclosure.

FIG. 10 is a vertical cross-sectional view of the exemplary structureafter formation of an insulating spacer according to an embodiment ofthe present disclosure.

FIG. 11A is a vertical cross-sectional view of the exemplary structureafter formation of a backside contact via structure and additionalcontact via structures according to an embodiment of the presentdisclosure.

FIG. 11B is a horizontal cross-sectional view of exemplary structure ofFIG. 11A along the horizontal plane B-B′ of FIG. 11A.

FIG. 11C is a vertical cross-sectional view of the exemplary structureof FIG. 11B along the vertical plane C-C′ of FIG. 11B.

FIG. 11D is a vertical cross-sectional view of the exemplary structureof FIG. 11B along the vertical plane D-D′ of FIG. 11B.

FIG. 11E is a magnified view of a region of FIG. 11B.

FIG. 12 is a simulated current voltage plot illustrating a difference inthe channel current through an outer device semiconductor channel and aninner device semiconductor channel due to presence of a doped pocketregion according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed tothree-dimensional memory structures, such as vertical NAND strings andother three-dimensional devices, and methods of making thereof, thevarious aspects of which are described below. The embodiments of thedisclosure can be employed to form various structures including amultilevel memory structure, non-limiting examples of which includesemiconductor devices such as three-dimensional monolithic memory arraydevices comprising a plurality of NAND memory strings. The drawings arenot drawn to scale. Multiple instances of an element may be duplicatedwhere a single instance of the element is illustrated, unless absence ofduplication of elements is expressly described or clearly indicatedotherwise. Ordinals such as “first,” “second,” and “third” are employedmerely to identify similar elements, and different ordinals may beemployed across the specification and the claims of the instantdisclosure. As used herein, a first element located “on” a secondelement can be located on the exterior side of a surface of the secondelement or on the interior side of the second element. As used herein, afirst element is located “directly on” a second element if there exist aphysical contact between a surface of the first element and a surface ofthe second element.

As used herein, a “layer” refers to a material portion including aregion having a substantially uniform thickness. A layer may extend overthe entirety of an underlying or overlying structure, or may have anextent less than the extent of an underlying or overlying structure.Further, a layer may be a region of a homogeneous or inhomogeneouscontiguous structure that has a thickness less than the thickness of thecontiguous structure. For example, a layer may be located between anypair of horizontal planes between, or at, a top surface and a bottomsurface of the contiguous structure. A layer may extend horizontally,vertically, and/or along a tapered surface. A substrate may be a layer,may include one or more layers therein, and/or may have one or morelayer thereupon, thereabove, and/or therebelow.

A monolithic three-dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as asemiconductor wafer, with no intervening substrates. The term“monolithic” means that layers of each level of the array are directlydeposited on the layers of each underlying level of the array. Incontrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device. For example,non-monolithic stacked memories have been constructed by forming memorylevels on separate substrates and vertically stacking the memory levels,as described in U.S. Pat. No. 5,915,167 titled “Three-dimensionalStructure Memory.” The substrates may be thinned or removed from thememory levels before bonding, but as the memory levels are initiallyformed over separate substrates, such memories are not true monolithicthree-dimensional memory arrays. The various three-dimensional memorydevices of the present disclosure include a monolithic three-dimensionalNAND string memory device, and can be fabricated employing the variousembodiments described herein.

Referring to FIG. 1, an exemplary structure according to an embodimentof the present disclosure is illustrated, which can be employed, forexample, to fabricate a device structure containing vertical NAND memorydevices. The exemplary structure includes a substrate, which can be asemiconductor substrate. The substrate can include a substratesemiconductor layer 9. The substrate semiconductor layer 9 is asemiconductor material layer, and can include at least one elementalsemiconductor material, at least one III-V compound semiconductormaterial, at least one II-VI compound semiconductor material, at leastone organic semiconductor material, or other semiconductor materialsknown in the art. The substrate can have a major surface 7, which canbe, for example, a topmost surface of the substrate semiconductor layer9. The major surface 7 can be a semiconductor surface. In oneembodiment, the major surface 7 can be a single crystallinesemiconductor surface.

As used herein, a “semiconductor material” refers to a material havingelectrical conductivity in the range from 1.0×10⁻⁶ S/cm to 1.0×10⁵ S/cm,and is capable of producing a doped material having electricalconductivity in a range from 1.0 S/cm to 1.0×10⁵ S/cm upon suitabledoping with an electrical dopant. As used herein, an “electrical dopant”refers to a p-type dopant that adds a hole to a valence band within aband structure, or an n-type dopant that adds an electron to aconduction band within a band structure. As used herein, a “conductivematerial” refers to a material having electrical conductivity greaterthan 1.0×10⁵ S/cm. As used herein, an “insulator material” or a“dielectric material” refers to a material having electricalconductivity less than 1.0×10⁻⁶ S/cm. All measurements for electricalconductivities are made at the standard condition. Optionally, at leastone doped well (not expressly shown) can be formed within the substratesemiconductor layer 9.

At least one semiconductor device for a peripheral circuitry can beformed on a portion of the substrate semiconductor layer 9. The at leastone semiconductor device can include, for example, field effecttransistors. For example, at least one shallow trench isolationstructure 120 can be formed by etching portions of the substratesemiconductor layer 9 and depositing a dielectric material therein. Agate dielectric layer, at least one gate conductor layer, and a gate capdielectric layer can be formed over the substrate semiconductor layer 9,and can be subsequently patterned to form at least one gate structure(150, 152, 154, 158), each of which can include a gate dielectric 150,at least one gate electrode (152, 154), and a gate cap dielectric. Agate electrode (152, 154) may include a stack of a first gate electrodeportion 152 and a second gate electrode portion 154. At least one gatespacer 156 can be formed around the at least one gate structure (150,152, 154, 158) by depositing and anisotropically etching a conformaldielectric layer. Active regions 130 can be formed in upper portions ofthe substrate semiconductor layer 9, for example, by introducingelectrical dopants employing the at least one gate structure (150, 152,154, 158) as masking structures. Additional masks may be employed asneeded. The active region 130 can include source regions and drainregions of field effect transistors. A first dielectric liner 161 and asecond dielectric liner 162 can be optionally formed. Each of the firstand second dielectric liners (161, 162) can comprise a silicon oxidelayer, a silicon nitride layer, and/or a dielectric metal oxide layer.In an illustrative example, the first dielectric liner 161 can be asilicon oxide layer, and the second dielectric liner 162 can be asilicon nitride layer. The least one semiconductor device for theperipheral circuitry can contain a driver circuit for memory devices tobe subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the atleast one semiconductor device, and can be subsequently planarized toform a planarization dielectric layer 170. In one embodiment theplanarized top surface of the planarization dielectric layer 170 can becoplanar with a top surface of the dielectric liners (161, 162).Subsequently, the planarization dielectric layer 170 and the dielectricliners (161, 162) can be removed from an area to physically expose a topsurface of the substrate semiconductor layer 9.

An optional semiconductor material layer 10 can be formed on the topsurface of the substrate semiconductor layer 9 by deposition of a singlecrystalline semiconductor material, for example, by selective epitaxy.The deposited semiconductor material can be the same as, or can bedifferent from, the semiconductor material of the substratesemiconductor layer 9. The deposited semiconductor material can be anymaterial that can be employed for the semiconductor substrate layer 9 asdescribed above. The single crystalline semiconductor material of thesemiconductor material layer 10 can be in epitaxial alignment with thesingle crystalline structure of the substrate semiconductor layer 9.Portions of the deposited semiconductor material located above the topsurface of the planarization dielectric layer 170 can be removed, forexample, by chemical mechanical planarization (CMP). In this case, thesemiconductor material layer 10 can have a top surface that is coplanarwith the top surface of the planarization dielectric layer 170.

At least a portion of the semiconductor material layer 10 located in thedevice region 100 is a doped well. As used herein, a “doped well” refersto a portion of a semiconductor material having a doping of a sameconductivity type (which can be p-type or n-type) and a substantiallysame level of dopant concentration throughout. The doped well can be thesame as the semiconductor material layer 10 or can be a portion of thesemiconductor material layer 10, or, in case the semiconductor materiallayer 10 is omitted, can be a portion of the substrate semiconductorlayer 9. The conductivity type of the doped well is herein referred toas a first conductivity type, which can be p-type or n-type. The dopantconcentration level of the doped well is herein referred to as a firstdopant concentration level. In one embodiment, the first dopantconcentration level can be in a range from 1.0×10¹⁵/cm³ to 1.0×10¹⁸/cm³,although lesser and greater dopant concentration levels can also beemployed. As used herein, a dopant concentration level refers to averagedopant concentration for a given region.

Optionally, a dielectric pad layer 12 can be formed above thesemiconductor material layer 10 and the planarization dielectric layer170. The dielectric pad layer 12 can be, for example, silicon oxidelayer. The thickness of the dielectric pad layer 12 can be in a rangefrom 3 nm to 30 nm, although lesser and greater thicknesses can also beemployed.

A dielectric cap layer 31 can be optionally formed. The dielectric caplayer 31 includes a dielectric material, and can be formed directly ontop surfaces of gate electrodes to be subsequently formed (at the levelof the bottommost spacer layer 42). Exemplary materials that can beemployed for the dielectric cap layer 31 include, but are not limitedto, silicon oxide, a dielectric metal oxide, and silicon nitride (incase the material of second material layers to be subsequently formed isnot silicon nitride). The dielectric cap layer 31 provides electricalisolation for the gate electrodes.

A stack of an alternating plurality of first material layers (which canbe insulating layers 32) and second material layers (which are referredto spacer material layers) is formed over the top surface of thesubstrate, which can be, for example, on the top surface of thedielectric cap layer 31. As used herein, a “material layer” refers to alayer including a material throughout the entirety thereof. As usedherein, a “spacer material layer” refers to a material layer that islocated between two other material layers, i.e., between an overlyingmaterial layer and an underlying material layer. As used herein, analternating plurality of first elements and second elements refers to astructure in which instances of the first elements and instances of thesecond elements alternate. Each instance of the first elements that isnot an end element of the alternating plurality is adjoined by twoinstances of the second elements on both sides, and each instance of thesecond elements that is not an end element of the alternating pluralityis adjoined by two instances of the first elements on both ends. Thefirst elements may have the same thickness thereamongst, or may havedifferent thicknesses. The second elements may have the same thicknessthereamongst, or may have different thicknesses. The alternatingplurality of first material layers and second material layers may beginwith an instance of the first material layers or with an instance of thesecond material layers, and may end with an instance of the firstmaterial layers or with an instance of the second material layers. Inone embodiment, an instance of the first elements and an instance of thesecond elements may form a unit that is repeated with periodicity withinthe alternating plurality. The spacer material layers can be formed aselectrically conductive layers, or can be replaced with electricallyconductive layers in a subsequent processing step.

Each first material layer includes a first material, and each secondmaterial layer includes a second material that is different from thefirst material. In one embodiment, each first material layer can be aninsulating layer 32, and each second material layer can be a sacrificialmaterial layer 42. In this case, the stack can include an alternatingplurality of insulating layers 32 and sacrificial material layers 42,and constitutes a prototype stack of alternating layers comprisinginsulating layers 32 and sacrificial material layers 42. As used herein,a “prototype” structure or an “in-process” structure refers to atransient structure that is subsequently modified in the shape orcomposition of at least one component therein.

The stack of the alternating plurality is herein referred to as analternating stack (32, 42). In one embodiment, the alternating stack(32, 42) can include insulating layers 32 composed of the firstmaterial, and sacrificial material layers 42 composed of a secondmaterial different from that of insulating layers 32. The first materialof the insulating layers 32 can be at least one insulating material. Assuch, each insulating layer 32 can be an insulating material layer.Insulating materials that can be employed for the insulating layers 32include, but are not limited to, silicon oxide (including doped orundoped silicate glass), silicon nitride, silicon oxynitride,organosilicate glass (OSG), spin-on dielectric materials, dielectricmetal oxides that are commonly known as high dielectric constant(high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.)and silicates thereof, dielectric metal oxynitrides and silicatesthereof, and organic insulating materials. In one embodiment, the firstmaterial of the insulating layers 32 can be silicon oxide.

The second material of the sacrificial material layers 42 is asacrificial material that can be removed selective to the first materialof the insulating layers 32. As used herein, a removal of a firstmaterial is “selective to” a second material if the removal processremoves the first material at a rate that is at least twice the rate ofremoval of the second material. The ratio of the rate of removal of thefirst material to the rate of removal of the second material is hereinreferred to as a “selectivity” of the removal process for the firstmaterial with respect to the second material.

The sacrificial material layers 42 may comprise an insulating material,a semiconductor material, or a conductive material. The second materialof the sacrificial material layers 42 can be subsequently replaced withelectrically conductive electrodes which can function, for example, ascontrol gate electrodes of a vertical NAND device. Non-limiting examplesof the second material include silicon nitride, an amorphoussemiconductor material (such as amorphous silicon), and apolycrystalline semiconductor material (such as polysilicon). In oneembodiment, the sacrificial material layers 42 can be spacer materiallayers that comprise silicon nitride or a semiconductor materialincluding at least one of silicon and germanium.

In one embodiment, the insulating layers 32 can include silicon oxide,and sacrificial material layers can include silicon nitride sacrificialmaterial layers. The first material of the insulating layers 32 can bedeposited, for example, by chemical vapor deposition (CVD). For example,if silicon oxide is employed for the insulating layers 32, tetraethylorthosilicate (TEOS) can be employed as the precursor material for theCVD process. The second material of the sacrificial material layers 42can be formed, for example, CVD or atomic layer deposition (ALD).

The sacrificial material layers 42 can be suitably patterned so thatconductive material portions to be subsequently formed by replacement ofthe sacrificial material layers 42 can function as electricallyconductive electrodes, such as the control gate electrodes of themonolithic three-dimensional NAND string memory devices to besubsequently formed. The sacrificial material layers 42 may comprise aportion having a strip shape extending substantially parallel to themajor surface 7 of the substrate.

The thicknesses of the insulating layers 32 and the sacrificial materiallayers 42 can be in a range from 20 nm to 50 nm, although lesser andgreater thicknesses can be employed for each insulating layer 32 and foreach sacrificial material layer 42. The number of repetitions of thepairs of an insulating layer 32 and a sacrificial material layer (e.g.,a control gate electrode or a sacrificial material layer) 42 can be in arange from 2 to 1,024, and typically from 8 to 256, although a greaternumber of repetitions can also be employed. The top and bottom gateelectrodes in the stack may function as the select gate electrodes. Inone embodiment, each sacrificial material layer 42 in the alternatingstack (32, 42) can have a uniform thickness that is substantiallyinvariant within each respective sacrificial material layer 42.

Optionally, an insulating cap layer 70 can be formed over thealternating stack (32, 42). The insulating cap layer 70 includes adielectric material that is different from the material of thesacrificial material layers 42. In one embodiment, the insulating caplayer 70 can include a dielectric material that can be employed for theinsulating layers 32 as described above. The insulating cap layer 70 canhave a greater thickness than each of the insulating layers 32. Theinsulating cap layer 70 can be deposited, for example, by chemical vapordeposition. In one embodiment, the insulating cap layer 70 can be asilicon oxide layer.

Subsequently, a lithographic material stack (not shown) including atleast a photoresist layer can be formed over the insulating cap layer 70and the alternating stack (32, 42), and can be lithographicallypatterned to form openings therein. The pattern in the lithographicmaterial stack can be transferred through the insulating cap layer 70and through entirety of the alternating stack (32, 42) by at least oneanisotropic etch that employs the patterned lithographic material stackas an etch mask. Portions of the alternating stack (32, 42) underlyingthe openings in the patterned lithographic material stack are etched toform memory openings 49. In other words, the transfer of the pattern inthe patterned lithographic material stack through the alternating stack(32, 42) forms the memory openings 49 that extend through thealternating stack (32, 42). The chemistry of the anisotropic etchprocess employed to etch through the materials of the alternating stack(32, 42) can alternate to optimize etching of the first and secondmaterials in the alternating stack (32, 42). The anisotropic etch canbe, for example, a series of reactive ion etches. Optionally, thedielectric cap layer 31 may be used as an etch stop layer between thealternating stack (32, 42) and the substrate. The sidewalls of thememory openings 49 can be substantially vertical, or can be tapered. Thepatterned lithographic material stack can be subsequently removed, forexample, by ashing.

The memory openings 49 are formed through the dielectric cap layer 31and the dielectric pad layer 12 so that the memory openings 49 extendfrom the top surface of the alternating stack (32, 42) to the topsurface of the semiconductor material layer 10 within the substratebetween the lower select gate electrodes. In one embodiment, an overetchinto the semiconductor material layer 10 may be optionally performedafter the top surface of the semiconductor material layer 10 isphysically exposed at a bottom of each memory opening 49. The overetchmay be performed prior to, or after, removal of the lithographicmaterial stack. In other words, the recessed surfaces of thesemiconductor material layer 10 may be vertically offset from theundressed top surfaces of the semiconductor material layer 10 by arecess depth. The recess depth can be, for example, in a range from 1 nmto 50 nm, although lesser and greater recess depths can also beemployed. The overetch is optional, and may be omitted. If the overetchis not performed, the bottom surface of each memory opening 49 can becoplanar with the topmost surface of the semiconductor material layer10. Each of the memory openings 49 can include a sidewall (or aplurality of sidewalls) that extends substantially perpendicular to thetopmost surface of the substrate. The region in which the array ofmemory openings 49 is formed is herein referred to as a device region.The substrate semiconductor layer 9 and the semiconductor material layer10 collectively constitutes a substrate (9, 10), which can be asemiconductor substrate. Alternatively, the semiconductor material layer10 may be omitted, and the memory openings 49 can be extend to a topsurface of the semiconductor material layer 10.

A memory stack structure can be formed in each of the memory openingemploying various embodiments of the present disclosure. FIGS. 2A-2Hillustrate sequential vertical cross-sectional views of a memory openingwithin the exemplary structure during formation of an exemplary memorystack structure according to a embodiment of the present disclosure.Formation of the exemplary memory stack structure can be performedwithin each of the memory openings 49 in the exemplary structureillustrated in FIG. 1.

Referring to FIG. 2A, a memory opening 49 in the exemplary structure ofFIG. 1 is illustrated in a magnified view. The memory opening 49 extendsthrough the insulating cap layer 70, the alternating stack (32, 42), thedielectric cap layer 31, the dielectric pad layer 12, and optionallyinto an upper portion of the semiconductor material layer 10. The recessdepth of the bottom surface of each memory opening with respect to thetop surface of the semiconductor material layer 10 can be in a rangefrom 0 nm to 30 nm, although greater recess depths can also be employed.Optionally, the sacrificial material layers 42 can be laterally recessedpartially to form lateral recesses (not shown), for example, by anisotropic etch.

Referring to FIG. 2B, an optional epitaxial channel portion 11 can beformed at the bottom portion of each memory opening 49, for example, byselective epitaxy. Each epitaxial channel portion 11 comprises a singlecrystalline semiconductor material in epitaxial alignment with thesingle crystalline semiconductor material of the semiconductor materiallayer 10. In one embodiment, the epitaxial channel portion 11 can bedoped with electrical dopants of the same conductivity type as thesemiconductor material layer 10. In one embodiment, the top surface ofeach epitaxial channel portion 11 can be formed above a horizontal planeincluding the top surface of a sacrificial material layer 42. In thiscase, at least one source select gate electrode can be subsequentlyformed by replacing each sacrificial material layer 42 located below thehorizontal plane including the top surfaces of the epitaxial channelportions 11 with a respective conductive material layer.

Referring to FIG. 2C, a series of layers including at least one blockingdielectric layer (501L, 503L), a memory material layer 504L, a tunnelingdielectric layer 506L, and an optional first semiconductor channel layer601L can be sequentially deposited in the memory openings 49. The atleast one blocking dielectric layer (501L, 503L) can include, forexample, a first blocking dielectric layer 501L and a second blockingdielectric layer 503L.

The first blocking dielectric layer 501L can be deposited on thesidewalls of each memory opening 49 by a conformal deposition method.The first blocking dielectric layer 501L includes a dielectric material,which can be a dielectric metal oxide. As used herein, a dielectricmetal oxide refers to a dielectric material that includes at least onemetallic element and at least oxygen. The dielectric metal oxide mayconsist essentially of the at least one metallic element and oxygen, ormay consist essentially of the at least one metallic element, oxygen,and at least one non-metallic element such as nitrogen. In oneembodiment, the first blocking dielectric layer 501L can include adielectric metal oxide having a dielectric constant greater than 7.9,i.e., having a dielectric constant greater than the dielectric constantof silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide(Al₂O₃), hafnium oxide (HfO₂), lanthanum oxide (LaO₂), yttrium oxide(Y₂O₃), tantalum oxide (Ta₂O₅), silicates thereof, nitrogen-dopedcompounds thereof, alloys thereof, and stacks thereof. The firstblocking dielectric layer 501L can be deposited, for example, bychemical vapor deposition (CVD), atomic layer deposition (ALD), pulsedlaser deposition (PLD), liquid source misted chemical deposition, or acombination thereof. The thickness of the first blocking dielectriclayer 501L can be in a range from 1 nm to 20 nm, although lesser andgreater thicknesses can also be employed. The first blocking dielectriclayer 501L can subsequently function as a dielectric material portionthat blocks leakage of stored electrical charges to control gateelectrodes. In one embodiment, the first blocking dielectric layer 501Lincludes aluminum oxide.

The second blocking dielectric layer 503L can be formed on the firstblocking dielectric layer 501L. The second blocking dielectric layer503L can include a dielectric material that is different from thedielectric material of the first blocking dielectric layer 501L. In oneembodiment, the second blocking dielectric layer 503L can includesilicon oxide (e.g., SiO₂), a dielectric metal oxide having a differentcomposition than the first blocking dielectric layer 501L, siliconoxynitride, silicon nitride, or a combination thereof. In oneembodiment, the second blocking dielectric layer 503L can includesilicon oxide. The second blocking dielectric layer 503L can be formedby a conformal deposition method such as low pressure chemical vapordeposition, atomic layer deposition, or a combination thereof. Thethickness of the second blocking dielectric layer 503L can be in a rangefrom 1 nm to 20 nm, although lesser and greater thicknesses can also beemployed. Alternatively, the first blocking dielectric layer 501L and/orthe second blocking dielectric layer 503L can be omitted, and a blockingdielectric layer can be formed after formation of backside recesses onsurfaces of memory films to be subsequently formed.

Subsequently, the memory material layer 504L, the tunneling dielectriclayer 506L, and the optional first semiconductor channel layer 601L canbe sequentially formed. In one embodiment, the memory material layer504L can be a charge trapping material including a dielectric chargetrapping material, which can be, for example, silicon nitride.Alternatively, the memory material layer 504L can include a conductivematerial such as doped polysilicon or a metallic material that ispatterned into multiple electrically isolated portions (e.g., floatinggates), for example, by being formed within lateral recesses intosacrificial material layers 42. In one embodiment, the memory materiallayer 504L includes a silicon nitride layer.

The memory material layer 504L can be formed as a single memory materiallayer of homogeneous composition, or can include a stack of multiplememory material layers. The multiple memory material layers, ifemployed, can comprise a plurality of spaced-apart floating gatematerial layers that contain conductive materials (e.g., metal such astungsten, molybdenum, tantalum, titanium, platinum, ruthenium, andalloys thereof, or a metal silicide such as tungsten silicide,molybdenum silicide, tantalum silicide, titanium silicide, nickelsilicide, cobalt silicide, or a combination thereof) and/orsemiconductor materials (e.g., polycrystalline or amorphoussemiconductor material including at least one elemental semiconductorelement or at least one compound semiconductor material). Alternativelyor additionally, the memory material layer 504L may comprise aninsulating charge trapping material, such as one or more silicon nitridesegments. Alternatively, the memory material layer 504L may compriseconductive nanoparticles such as metal nanoparticles, which can be, forexample, ruthenium nanoparticles. The memory material layer 504L can beformed, for example, by chemical vapor deposition (CVD), atomic layerdeposition (ALD), physical vapor deposition (PVD), or any suitabledeposition technique for storing electrical charges therein. Thethickness of the memory material layer 504L can be in a range from 2 nmto 20 nm, although lesser and greater thicknesses can also be employed.

The tunneling dielectric layer 506L includes a dielectric materialthrough which charge tunneling can be performed under suitableelectrical bias conditions. The charge tunneling may be performedthrough hot-carrier injection or by Fowler-Nordheim tunneling inducedcharge transfer depending on the mode of operation of the monolithicthree-dimensional NAND string memory device to be formed. The tunnelingdielectric layer 506L can include silicon oxide, silicon nitride,silicon oxynitride, dielectric metal oxides (such as aluminum oxide andhafnium oxide), dielectric metal oxynitride, dielectric metal silicates,alloys thereof, and/or combinations thereof. In one embodiment, thetunneling dielectric layer 506L can include a stack of a first siliconoxide layer, a silicon oxynitride layer, and a second silicon oxidelayer, which is commonly known as an ONO stack. In one embodiment, thetunneling dielectric layer 506L can include a silicon oxide layer thatis substantially free of carbon or a silicon oxynitride layer that issubstantially free of carbon. The thickness of the tunneling dielectriclayer 506L can be in a range from 2 nm to 20 nm, although lesser andgreater thicknesses can also be employed.

The optional first semiconductor channel layer 601L includes asemiconductor material such as at least one elemental semiconductormaterial, at least one III-V compound semiconductor material, at leastone II-VI compound semiconductor material, at least one organicsemiconductor material, or other semiconductor materials known in theart. In one embodiment, the first semiconductor channel layer 601Lincludes amorphous silicon or polysilicon. The first semiconductorchannel layer 601L can be formed by a conformal deposition method suchas low pressure chemical vapor deposition (LPCVD). The thickness of thefirst semiconductor channel layer 601L can be in a range from 2 nm to 10nm, although lesser and greater thicknesses can also be employed. Acavity 49′ is formed in the volume of each memory opening 49 that is notfilled with the deposited material layers (501L, 503L, 504L, 506 l,601L).

Referring to FIG. 2D, the optional first semiconductor channel layer601L, the tunneling dielectric layer 506L, the memory material layer504L, the at least one blocking dielectric layer (501L, 503L) aresequentially anisotropically etched employing at least one anisotropicetch process. The portions of the first semiconductor channel layer601L, the tunneling dielectric layer 506L, the memory material layer504L, and the at least one blocking dielectric layer (501L, 503L)located above the top surface of the insulating cap layer 70 can beremoved by the at least one anisotropic etch process. Further, thehorizontal portions of the first semiconductor channel layer 601L, thetunneling dielectric layer 506L, the memory material layer 504L, and theat least one blocking dielectric layer (501L, 503L) at a bottom of eachcavity 49′ can be removed to form openings in remaining portionsthereof. Each of the first semiconductor channel layer 601L, thetunneling dielectric layer 506L, the memory material layer 504L, and theat least one blocking dielectric layer (501L, 503L) can be etched byanisotropic etch process.

Each remaining portion of the first semiconductor channel layer 601Lconstitutes a first semiconductor channel portion 601. Each remainingportion of the tunneling dielectric layer 506L constitutes a tunnelingdielectric 506. Each remaining portion of the memory material layer 504Lis herein referred to as a charge storage element 504. In oneembodiment, the charge storage element 504 can be a contiguous layer,i.e., can be a charge storage layer. Each remaining portion of thesecond blocking dielectric layer 503L is herein referred to as a secondblocking dielectric 503. Each remaining portion of the first blockingdielectric layer 501L is herein referred to as a first blockingdielectric 501. A surface of the epitaxial channel portion 11 can bephysically exposed underneath the opening through the firstsemiconductor channel portion 601, the tunneling dielectric 506, thecharge storage element 504, and the at least one blocking dielectric(501, 503). If the epitaxial channel portion 11 is not present, a topsurface of the semiconductor material layer 10 can be physically exposedunderneath the memory cavity 49′. Optionally, the physically exposedportion of the epitaxial channel portion 11 can be vertically recessed.A tunneling dielectric 506 is surrounded by a charge storage element504. The charge storage element 504 can comprise a charge trappingmaterial or a floating gate material.

The set of the tunneling dielectric 506, the charge storage element 504,the second blocking dielectric 503, and the first blocking dielectric501 collectively constitutes a memory film 50. In one embodiment, thefirst semiconductor channel portion 601, the tunneling dielectric 506,the charge storage element 504, the second blocking dielectric 503, andthe first blocking dielectric 501 can have vertically coincidentsidewalls. As used herein, a first surface is “vertically coincident”with a second surface if there exists a vertical plane including boththe first surface and the second surface. Such a vertical plane may, ormay not, have a horizontal curvature, but does not include any curvaturealong the vertical direction, i.e., extends straight up and down.

Referring to FIG. 2E, a second semiconductor channel layer 602L can bedeposited directly on the semiconductor surface of the epitaxial channelportion 11 over the substrate (9, 10), and directly on the firstsemiconductor channel portion 601. The second semiconductor channellayer 602L includes a semiconductor material such as at least oneelemental semiconductor material, at least one III-V compoundsemiconductor material, at least one II-VI compound semiconductormaterial, at least one organic semiconductor material, or othersemiconductor materials known in the art. In one embodiment, the secondsemiconductor channel layer 602L includes amorphous silicon orpolysilicon. The second semiconductor channel layer 602L can be formedby a conformal deposition method such as low pressure chemical vapordeposition (LPCVD). The thickness of the second semiconductor channellayer 602L can be in a range from 2 nm to 10 nm, although lesser andgreater thicknesses can also be employed. The second semiconductorchannel layer 602L may partially fill the cavity 49′ in each memoryopening, or may fully fill the cavity in each memory opening.

The materials of the first semiconductor channel portion 601 and thesecond semiconductor channel layer 602L are collectively referred to asa semiconductor channel material. In other words, the semiconductorchannel material is a set of all semiconductor material in the firstsemiconductor channel portion 601 and the second semiconductor channellayer 602L.

Referring to FIG. 2F, in case the cavity 49′ in each memory opening isnot completely filled by the second semiconductor channel layer 602L, adielectric core layer 62L can be deposited in the cavity 49′ to fill anyremaining portion of the cavity 49′ within each memory opening. Thedielectric core layer 62L includes a dielectric material such as siliconoxide or organosilicate glass. The dielectric core layer 62L can bedeposited by a conformal deposition method such as low pressure chemicalvapor deposition (LPCVD), or by a self-planarizing deposition processsuch as spin coating.

Referring to FIG. 2G, the horizontal portion of the dielectric corelayer 62L can be removed, for example, by a recess etch from above thetop surface of the insulating cap layer 70. Further, the horizontalportion of the second semiconductor channel layer 602L located above thetop surface of the insulating cap layer 70 can be removed by aplanarization process, which can employ a recess etch or chemicalmechanical planarization (CMP). Each remaining portion of the secondsemiconductor channel layer 602L within a memory opening constitutes asecond semiconductor channel portion 602.

Each adjoining pair of a first semiconductor channel portion 601 and asecond semiconductor channel portion 602 can collectively form asemiconductor channel 60 through which electrical current can flow whena vertical NAND device including the semiconductor channel 60 is turnedon. A tunneling dielectric 506 is embedded within a charge storageelement 504, and laterally surrounds a portion of the semiconductorchannel 60. Each adjoining set of a first blocking dielectric 501, asecond blocking dielectric 503, a charge storage element 504, and atunneling dielectric 506 collectively constitute a memory film 50, whichcan store electrical charges with a macroscopic retention time. In someembodiments, a first blocking dielectric 501 and/or a second blockingdielectric 503 may not be present in the memory film 50 at this step,and a blocking dielectric may be subsequently formed after formation ofbackside recesses. As used herein, a macroscopic retention time refersto a retention time suitable for operation of a memory device as apermanent memory device such as a retention time in excess of 24 hours.

The top surface of the remaining portion of the dielectric core layer62L can be further recessed within each memory opening, for example, bya recess etch to a depth that is located between the top surface of theinsulating cap layer 70 and the bottom surface of the insulating caplayer 70. Each remaining portion of the dielectric core layer 62Lconstitutes a dielectric core 62.

Referring to FIG. 2H, drain regions 63 can be formed by depositing adoped semiconductor material within each recessed region above thedielectric cores 62. The doped semiconductor material can be, forexample, doped polysilicon. Excess portions of the depositedsemiconductor material can be removed from above the top surface of theinsulating cap layer 70, for example, by chemical mechanicalplanarization (CMP) or a recess etch to form the drain regions 63.

The exemplary memory stack structure can be embedded into the exemplarystructure illustrated in FIG. 1. FIG. 3 illustrates the exemplarystructure that incorporates multiple instances of the exemplary memorystack structure of FIG. 2H. The exemplary structure includes asemiconductor device, which comprises a stack (32, 42) including analternating plurality of material layers (e.g., the sacrificial materiallayers 42) and insulating layers 32 located over a semiconductorsubstrate (9, 10), and a memory opening extending through the stack (32,42). The semiconductor device further comprises a first blockingdielectric 501 vertically extending from a bottommost layer (e.g., thebottommost sacrificial material layer 42) of the stack to a topmostlayer (e.g., the topmost sacrificial material layer 42) of the stack,and contacting a sidewall of the memory opening and a horizontal surfaceof the semiconductor substrate. While the present disclosure isdescribed employing the illustrated configuration for the memory stackstructure, the methods of the present disclosure can be applied toalternative memory stack structures including a polycrystallinesemiconductor channel.

Referring to FIG. 4, an optional first contact level dielectric layer 71can be formed over the substrate (9, 10). As an optional structure, thefirst contact level dielectric layer 71 may, or may not, be formed. Incase the first contact level dielectric layer 71 is formed, the firstcontact level dielectric layer 71 includes a dielectric material such assilicon oxide, silicon nitride, silicon oxynitride, porous or non-porousorganosilicate glass (OSG), or a combination thereof. If anorganosilicate glass is employed, the organosilicate glass may, or maynot, be doped with nitrogen. The first contact level dielectric layer 71can be formed over a horizontal plane including the top surface of theinsulating cap layer 70 and the top surfaces of the drain regions 63.The first contact level dielectric layer 71 can be deposited by chemicalvapor deposition, atomic layer deposition (ALD), spin-coating, or acombination thereof. The thickness of the first contact level dielectriclayer 71 can be in a range from 10 nm to 300 nm, although lesser andgreater thicknesses can also be employed.

In one embodiment, the first contact level dielectric layer 71 can beformed as a dielectric material layer having a uniform thicknessthroughout. The first contact level dielectric layer 71 may be formed asa single dielectric material layer, or can be formed as a stack of aplurality of dielectric material layers. Alternatively, formation of thefirst contact level dielectric layer 71 may be merged with formation ofat least one line level dielectric layer (not shown). While the presentdisclosure is described employing an embodiment in which the firstcontact level dielectric layer 71 is a structure separate from anoptional second contact level dielectric layer or at least one linelevel dielectric layer to be subsequently deposited, embodiments inwhich the first contact level dielectric layer 71 and at least one linelevel dielectric layer are formed at a same processing step, and/or as asame material layer, are expressly contemplated herein.

Optionally, a portion of the alternating stack (32, 42) can be removed,for example, by applying and patterning a photoresist layer with anopening and by transferring the pattern of the opening through thealternating stack (32, 42) employing an etch such as an anisotropicetch. An optional trench extending through the entire thickness of thealternating stack (32, 42) can be formed within an area that includes aperipheral device region 200 and a portion of a contact region 300,which is adjacent to a device region 100 that includes an array ofmemory stack structures 55. Subsequently, the trench can be filled withan optional dielectric material such as silicon oxide. Excess portionsof the dielectric material can be removed from above the top surface ofthe first contact level dielectric layer 71 by a planarization processsuch as chemical mechanical planarization and/or a recess etch. The topsurfaces of the first contact level dielectric layer 71 can be employedas a stopping surface during the planarization. The remaining dielectricmaterial in the trench constitutes a dielectric material portion 64.

A stepped cavity can be formed within the contact region 300, which canstraddle the dielectric material portion 64 and a portion of thealternating stack (32, 42). Alternatively, the dielectric materialportion 64 may be omitted and the stepped cavity 69 may be formeddirectly in the stack (32, 42). The stepped cavity can have variousstepped surfaces such that the horizontal cross-sectional shape of thestepped cavity changes in steps as a function of the vertical distancefrom the top surface of the substrate (9, 10). In one embodiment, thestepped cavity can be formed by repetitively performing a set ofprocessing steps. The set of processing steps can include, for example,an etch process of a first type that vertically increases the depth of acavity by one or more levels, and an etch process of a second type thatlaterally expands the area to be vertically etched in a subsequent etchprocess of the first type. As used herein, a “level” of a structureincluding alternating plurality is defined as the relative position of apair of a first material layer and a second material layer within thestructure.

The dielectric material portion 64 can have stepped surfaces afterformation of the stepped cavity, and a peripheral portion of thealternating stack (32, 42) can have stepped surfaces after formation ofthe stepped cavity. As used herein, “stepped surfaces” refer to a set ofsurfaces that include at least two horizontal surfaces and at least twovertical surfaces such that each horizontal surface is adjoined to afirst vertical surface that extends upward from a first edge of thehorizontal surface, and is adjoined to a second vertical surface thatextends downward from a second edge of the horizontal surface. A“stepped cavity” refers to a cavity having stepped surfaces.

A retro-stepped dielectric material portion 65 (i.e., an insulating fillmaterial portion) can be formed in the stepped cavity by deposition of adielectric material therein. A dielectric material such as silicon oxidecan be deposited in the stepped cavity. Excess portions of the depositeddielectric material can be removed from above the top surface of thefirst contact level dielectric layer 71, for example, by chemicalmechanical planarization (CMP). The remaining portion of the depositeddielectric material filling the stepped cavity constitutes theretro-stepped dielectric material portion 65. As used herein, a“retro-stepped” element refers to an element that has stepped surfacesand a horizontal cross-sectional area that increases monotonically as afunction of a vertical distance from a top surface of a substrate onwhich the element is present. If silicon oxide is employed for theretro-stepped dielectric material portion 65, the silicon oxide of theretro-stepped dielectric material portion 65 may, or may not, be dopedwith dopants such as B, P, and/or F.

Referring to FIGS. 5A and 5B, at least one dielectric support pillar 7Pmay be optionally formed through the retro-stepped dielectric materialportion 65 and/or through the first contact level dielectric layer 71and/or through the alternating stack (32, 42). The plane A-A′ in FIG. 5Bcorresponds to the plane of the vertical cross-sectional view of FIG.5A. In one embodiment, the at least one dielectric support pillar 7P canbe formed in the contact region 300, which is located adjacent to thedevice region 100. The at least one dielectric support pillar 7P can beformed, for example, by forming an opening extending through theretro-stepped dielectric material portion 65 and/or through thealternating stack (32, 42) and at least to the top surface of thesubstrate (9, 10), and by filling the opening with a dielectric materialthat is resistant to the etch chemistry to be employed to remove thesacrificial material layers 42.

In one embodiment, the at least one dielectric support pillar 7P caninclude silicon oxide and/or a dielectric metal oxide such as aluminumoxide. In one embodiment, the portion of the dielectric material that isdeposited over the first contact level dielectric layer 71 concurrentlywith deposition of the at least one dielectric support pillar 7P can bepresent over the first contact level dielectric layer 71 as a secondcontact level dielectric layer 73. Each of the at least one dielectricsupport pillar 7P and the second contact level dielectric layer 73 is anoptional structure. As such, the second contact level dielectric layer73 may, or may not, be present over the insulating cap layer 70 and theretro-stepped dielectric material portion 65. The first contact leveldielectric layer 71 and the second contact level dielectric layer 73 areherein collectively referred to as at least one contact level dielectriclayer (71, 73). In one embodiment, the at least one contact leveldielectric layer (71, 73) can include both the first and second contactlevel dielectric layers (71, 73), and optionally include any additionalvia level dielectric layer that can be subsequently formed. In anotherembodiment, the at least one contact level dielectric layer (71, 73) caninclude only the first contact level dielectric layer 71 or the secondcontact level dielectric layer 73, and optionally include any additionalvia level dielectric layer that can be subsequently formed.Alternatively, formation of the first and second contact leveldielectric layers (71, 73) may be omitted, and at least one via leveldielectric layer may be subsequently formed, i.e., after formation of abackside contact via structure.

The second contact level dielectric layer 73 and the at least onedielectric support pillar 7P can be formed as a single contiguousstructure of integral construction, i.e., without any material interfacetherebetween. In another embodiment, the portion of the dielectricmaterial that is deposited over the first contact level dielectric layer71 concurrently with deposition of the at least one dielectric supportpillar 7P can be removed, for example, by chemical mechanicalplanarization or a recess etch. In this case, the second contact leveldielectric layer 73 is not present, and the top surface of the firstcontact level dielectric layer 71 can be physically exposed.

Memory contact via structures 88 can be formed through the first andsecond contact level dielectric layers (73, 71). Specifically, aphotoresist layer can be applied over the second contact leveldielectric layer 73, and can be lithographically patterned to formopenings overlying the drain structures 63. An anisotropic etch can beperformed to transfer the pattern in the photoresist layer through thefirst and second contact level dielectric layers (73, 71) to form memorycontact via cavities that extend through the first and second contactlevel dielectric layers (73, 71). The memory contact via cavities can befilled with at least one conductive material. Excess portions of the atleast one conductive material can be removed from above a horizontalplane including a top surface of the second contact level dielectriclayer 73. Each remaining contiguous portion of the at least oneconductive material constitutes a memory contact via structure 88, whichcontacts a top surface of an underlying drain region 63. The photoresistlayer can be subsequently removed, for example, by ashing.Alternatively, the memory contact structures 88 may be formed at a laterstep such as a step corresponding to FIGS. 11A-11E.

Another photoresist layer (not shown) can be applied over thealternating stack (32, 42) and/or the retro-stepped dielectric materialportion 65, and optionally over the and lithographically patterned toform at least one backside contact trench 79 in an area in whichformation of a backside contact via structure is desired. The pattern inthe photoresist layer can be transferred through the alternating stack(32, 42) and/or the retro-stepped dielectric material portion 65employing an anisotropic etch to form the at least one backside contacttrench 79, which extends at least to the top surface of the substrate(9, 10). In one embodiment, the at least one backside contact trench 79can include a source contact opening in which a source contact viastructure can be subsequently formed.

Each backside contact trench 79 extends through the alternating stack(32, 42) and to the substrate (9, 10). Two ion implantation processescan be performed to form an implant region 250 in a portion of thesubstrate (9, 10) (which may be a portion of the semiconductor materiallayer 10) that underlies each the backside contact trench 79. As usedherein, a first element underlies a second element if a vertical lineperpendicular to the top substrate surface 7 passes through both firstand second elements. The two ion implantation process includes a p-typedopant implantation process that implants a p-type dopant such as boron,and an n-type dopant implantation process that implants an n-type dopantsuch as arsenic or phosphorus.

In one embodiment, the species of the p-type dopants and the n-typedopants are selected such that the dopants of the first conductivitytype (which is the conductivity type of the doped well in thesemiconductor material layer 10) has a greater diffusivity at anelevated temperature to be employed for a subsequent anneal process thandopants of the second conductivity type (which is the opposite of thefirst conductivity type) at the elevated temperature. In one embodiment,the first conductivity type can be p-type, and the p-type dopantsimplanted to form the implant region 250 can include boron atoms, andthe n-type dopants implanted to form the implant region 250 can includearsenic atoms and/or phosphorus atoms. The dose of the dopants of thefirst conductivity type can be the same as, can be greater than, or canbe less than, the dose of the dopants of the second conductivity type,provided that a region located directly underneath a backside contacttrench 79 can form a source region having a net doping of the secondconductivity type.

The atomic concentration of the dopants of the first conductivity typein the implant region 250 may be in a range from 1.0×10¹⁶/cm³ to5×10¹⁸/cm³, such as 1.0×10¹⁷/cm³ to 5.0×10¹⁷/cm³ although lesser andgreater atomic concentrations can also be employed. The atomicconcentration of the dopants of the second conductivity type in theimplant region may be in a range from 1.0×10¹⁹/cm³ to 5.0×10²¹/cm³,although lesser and greater atomic concentrations can also be employed.The order of the implantation process that implants the dopants of thefirst conductivity type and the implantation process that implants thedopants of the second conductivity type may be arbitrarily selected. Inan illustrative example, boron can be employed as dopants of the firstconductivity type. Implantation energy in a range from 5 keV to 20 keV,and a dose in a range from 1.0×10¹⁴/cm² to 3.0×10¹⁴/cm² can be employed.In an illustrative example, arsenic can be employed as dopants of thesecond conductivity type Implantation energy in a range from 20 keV to40 keV, and a dopse in a range from 1.0×10¹⁵/cm² to 2.0×10¹⁵/cm² can beemployed. Therefore, at least one, and preferably both of theimplantation energy and dose for the ions of the first conductivity typeare smaller than the implantation energy and dose for the ions of thesecond conductivity type.

Referring to FIGS. 6A-6D, an anneal process is performed at an elevatedtemperature to outdiffuse the p-type dopants and the n-type dopants. Theelevated temperature can be in a range from 600 degrees Celsius to 1,150degrees Celsius, although lesser and greater temperatures can also beemployed. The p-type and n-type dopants, i.e., the dopants of the firstconductivity type and the dopants of the second conductivity type,outdiffuse simultaneously from the implant region 250 during the annealprocess.

Dopants of the first conductivity type outdiffuse faster and fartherthan dopants of the second conductivity type to form a doped pocketregion 260. The doped pocket region 260 has a doping of the firstconductivity type, and includes dopants of the first conductivity typeat a second dopant concentration that is higher than the first dopantconcentration level of the doped well region, which is a portion of thesemiconductor material layer 10 that contacts the doped pocket region260. The second dopant concentration level in region 260 can be in arange from 1.0×10¹⁶/cm³ to 1.0×10²⁰/cm³, including 1.0×10¹⁷/cm³ to5.0×10¹⁸/cm³ although lesser and greater dopant concentration levels canalso be employed. The ratio of the second dopant concentration level tothe first dopant concentration level can be in a range from 3 to 300,although lesser and greater ratios can also be employed. In oneembodiment, the dopants in the doped pocket region 260 can consist ofdopants of the first conductivity type.

Dopants of the second conductivity type outdiffuse slower than dopantsof the first conductivity type. A source region 270 having a doping ofthe second conductivity type is formed within the pocket region 260 thatunderlies each backside contact trench 79. The source region 270includes dopants of the first conductivity type and dopants of thesecond conductivity type. The atomic concentration of the dopants of thesecond conductivity type is greater than the atomic concentration of thedopants of the first conductivity type in the source region 270 due togreater outdiffusion of dopants of the first conductivity type away fromthe region underlying the backside contact trench 79 and/or die to adifference in the implant dose and/or depth for the dopants of the firstand the second conductivity type. The doping of the source region 270 isdetermined by the difference between the atomic concentration of dopantsof the second conductivity type and the atomic concentration of dopantsof the first conductivity type, which is positive within the sourceregion 270 and is negative within the doped pocket region 260. The netconcentration level of dopants of the second conductivity type in thesource region 270, which is the average of the difference of the atomicconcentration of dopants of the second conductivity type and the atomicconcentration of dopants of the first conductivity type in the sourceregion 270, can be in a range from 1.0×10¹⁹/cm³ to 2.0×10²¹/cm³,although lesser and greater dopant concentration levels can also beemployed.

In an illustrative example, boron can be employed as dopants of thefirst conductivity type. The distance of lateral diffusion of boron canbe in a range from 100 nm to 150 nm, and a peak concentration of boronwithin the source region can be in a range from 1.0×10¹⁷/cm² to5.0×10¹⁷/cm², although lesser and greater lateral diffusion distancesand/or lesser and greater peak dopant concentrations can also beemployed. The depth of the pocket region 260 can be in a range from 250nm to 400 nm, although lesser and greater depths can also be employed.

In an illustrative example, arsenic can be employed as dopants of thesecond conductivity type. A peak concentration of arsenic within thesource region can be about 1.0×10²⁰/cm² to 5.0×10²⁰/cm², although lesserand greater lateral diffusion distances and/or lesser and greater peakdopant concentrations can also be employed. The depth of the sourceregion 270 can be in a range from 100 nm to 150 nm, although lesser andgreater depths can also be employed.

The process parameters of the ion implantation process and/or of theanneal process, including the elevated temperature of the anneal processand the duration of the anneal process at the elevated temperature, canbe selected such that an interface 261 between the doped pocket region260 and the doped well in layer 10 is located underneath first (outer)memory stack structures 55 overlying an outer epitaxial channel portion11O, and is not formed underneath second (inner) memory stack structures55 overlying an inner epitaxial channel portion 11I. The first (outer)memory stack structures 55 are located closer to the nearest trench 79than the second (inner) memory stack structures. If the optionalepitaxial channel portions 11 are present, then the first (outer)epitaxial channel portions 11I are located closer to the nearest trench79 than the second (inner) epitaxial channel portions 11O. In onenon-limiting embodiment, the outer epitaxial channel portions 11Ocomprise a subset of the epitaxial channel portions 11 for which thelateral separation distance from a most proximal backside contact trench79 does not exceed the sum of the minimum separation distance betweenthe most proximal backside contact trench 79 and the epitaxial channelportions 11 and one half of the maximum lateral dimension MLD (i.e.,diameter of portion 11 divided by two), of an epitaxial channel portion11. The lateral separation distance for an outer epitaxial channelportion 11O is herein referred to as a first lateral separation distanceLSD1. Inner epitaxial channel portions 11I refer to the subset of theepitaxial channel portions 11 for which the lateral separation distancefrom a most proximal backside contact trench 79 exceed the sum of theminimum separation distance between the most proximal backside contacttrench 79 and the epitaxial channel portions 11 and one half of themaximum lateral dimension MLD of an epitaxial channel portion 11. Thelateral separation distance for an inner epitaxial channel portion 11Iis herein referred to as a second lateral separation distance LSD2. Ifepitaxial channel portions are omitted, then the memory stack structures55 overly layer 10 rather than portion 11, and the distances LSD1 andLSD2 are measured between the structures 55 and the trench 79, anddimension MLD is the diameter at the height midpoint of the structures55.

For at least one of the outer epitaxial channel portion 11O, the lateralseparation distance is the same as the minimum separation distance fromthe most proximal backside contact trench 79. In case the memory stackstructures 55 are arranged in a periodic two-dimensional array, and thedirection of periodicity is the same as the lengthwise direction of themost proximal backside contact trench 79, the outer epitaxial channelportions 11O within a same row can have the same first lateralseparation distance LSD1, which is the same as the minimum separationdistance from the backside contact trench 79. The inner epitaxialchannel portions 11I can have different second lateral separationdistances LSD2 (which are greater than distances LSD1) depending on therow in which each respective inner epitaxial channel portion 11I islocated.

Each memory stack structure 55 overlying an outer epitaxial channelportion 11O is herein referred to as a first memory stack structure, oran outer memory stack structure. Each memory stack structure 55overlying an inner epitaxial channel portion 11I is herein referred toas a second memory stack structure, or an inner memory stack structure.In one embodiment, the process parameters of the anneal process can beselected such that the interface 261 between the doped pocket region 260and the doped well (located within the semiconductor material layer 10)underlies each of the first memory stack structures among the pluralityof memory stack structures 55.

In one embodiment, the process conditions of the anneal process areselected such that the doped pocket region 260 does not underlie any ofthe second (inner) memory stack structures, but underlies at least aportion of the first (outer) memory stack structures among the pluralityof memory stack structures 55. Each of the plurality of memory stackstructures 55 comprises a semiconductor channel 60 of a respectivetransistor. In one embodiment, the process conditions of the annealprocess can be selected such that the difference between the meanthreshold voltage of the first memory stack structures and the meanthreshold voltage of the second memory stack structure is not greaterthan 0.5 V, such as 0 to 0.5V, for example 0.1 to 0.25V. The mechanismfor providing such uniform distribution of threshold voltages for thetransistors of the first and second memory stack structures 55 isdiscussed below.

The doped pocket region 260 laterally surrounds the source region 270.Further, the bottom surface of the source region 270 can be verticallyspaced from the doped well (within the semiconductor material layer 10)by a horizontal portion of the doped pocket region 260. In oneembodiment the thickness of the horizontal portion of the doped pocketregion 260 can be substantially the same as the least distance betweenan inner sidewall adjacent to source region 270 and an outer sidewall(i.e., interface 261) of the doped pocket region 260.

In one embodiment, the first conductivity type can be p-type, the secondconductivity type can be n-type, the doped pocket region 260 cancomprise boron as dopants of the first conductivity type, and the sourceregion 270 can comprises boron and at least one of arsenic andphosphorus such that the atomic concentration of the n-type dopants isgreater than the atomic concentration of the p-type dopants within thesource region 270.

The epitaxial channel portions 11 have a doping of the firstconductivity type. The epitaxial channel portions 11 (as provided byin-situ doping during formation of the epitaxial channel portions 11 ata processing step of FIG. 2B) can be heavily doped, e.g., at an atomicconcentration in a range from 1.0×10¹⁹/cm³ to 1.0×10²¹/cm³. Thus, thethreshold voltage of the field effect transistors in each memory stackstructure 55 is not determined by the dopant concentration of theepitaxial channel portions 11, but is determined by the dopant profilewithin the horizontal portions of each semiconductor channel thatextends to a most proximal source region 270. Thus, the dopant profilein the doped pocket region 260 and the doped well determines thethreshold voltage of the field effect transistors. Specifically, thethreshold voltage of each transistor including a semiconductor channel60 as a component of the channel can be determined by the geometry andthe dopant concentration of the pocket region 260. By providing an arealoverlap between the area of the doped pocket region 260 and the first(outer) memory stack structures while not providing any overlap betweenthe area of the doped pocket region 260 and the second (inner) memorystack structures, the threshold voltages of the transistors of verticalmemory devices can be within a predefined tolerance limit (which can be,for example, less than 0.5 V between the transistors including a channelextending through a first memory stack structure and the transistorsincluding a channel extending through a second memory stack structure).The mechanism for controlling the threshold voltages at, or around, atarget is discussed below with respect to FIGS. 11A-12 after the finalstructure of the devices of the present disclosure is described.

Referring to FIG. 7, an etchant that selectively etches the secondmaterial of the sacrificial material layers 42 with respect to the firstmaterial of the insulating layers 32 can be introduced into the at leastone backside contact trench 79, for example, employing an etch process.Backside recesses 43 are formed in volumes from which the sacrificialmaterial layers 42 are removed. The removal of the second material ofthe sacrificial material layers 42 can be selective to the firstmaterial of the insulating layers 32, the material of the at least onedielectric support pillar 7P, the material of the retro-steppeddielectric material portion 65, the semiconductor material of thesemiconductor material layer 10, and the material of the outermost layerof the memory films 50. In one embodiment, the sacrificial materiallayers 42 can include silicon nitride, and the materials of theinsulating layers 32, the at least one dielectric support pillar 7P, andthe retro-stepped dielectric material portion 65 can be selected fromsilicon oxide and dielectric metal oxides. In another embodiment, thesacrificial material layers 42 can include a semiconductor material suchas polysilicon, and the materials of the insulating layers 32, the atleast one dielectric support pillar 7P, and the retro-stepped dielectricmaterial portion 65 can be selected from silicon oxide, silicon nitride,and dielectric metal oxides. In this case, the depth of the at least onebackside contact trench 79 can be modified so that the bottommostsurface of the at least one backside contact trench 79 is located withinthe dielectric pad layer 12, i.e., to avoid physical exposure of the topsurface of the semiconductor substrate layer 10.

The etch process that removes the second material selective to the firstmaterial and the outermost layer of the memory films 50 can be a wetetch process employing a wet etch solution, or can be a gas phase (dry)etch process in which the etchant is introduced in a vapor phase intothe at least one backside contact trench 79. For example, if thesacrificial material layers 42 include silicon nitride, the etch processcan be a wet etch process in which the exemplary structure is immersedwithin a wet etch tank including phosphoric acid, which etches siliconnitride selective to silicon oxide, silicon, and various other materialsemployed in the art. The at least one dielectric support pillar 7P, theretro-stepped dielectric material portion 65, and the memory stackstructures 55 provide structural support while the backside recesses 43are present within volumes previously occupied by the sacrificialmaterial layers 42.

Each backside recess 43 can be a laterally extending cavity having alateral dimension that is greater than the vertical extent of thecavity. In other words, the lateral dimension of each backside recess 43can be greater than the height of the backside recess 43. A plurality ofbackside recesses 43 can be formed in the volumes from which the secondmaterial of the sacrificial material layers 42 is removed. The memoryopenings in which the memory stack structures 55 are formed are hereinreferred to as front side recesses or front side cavities in contrastwith the backside recesses 43. In one embodiment, the device region 100comprises an array of monolithic three-dimensional NAND strings having aplurality of device levels disposed above the substrate (9, 10). In thiscase, each backside recess 43 can define a space for receiving arespective word line of the array of monolithic three-dimensional NANDstrings.

Each of the plurality of backside recesses 43 can extend substantiallyparallel to the top surface of the substrate (9, 10). A backside recess43 can be vertically bounded by a top surface of an underlyinginsulating layer 32 and a bottom surface of an overlying insulatinglayer 32. In one embodiment, each backside recess 43 can have a uniformheight throughout. Optionally, a backside blocking dielectric layer canbe formed in the backside recesses.

Physically exposed surface portions of epitaxial channel portions 11 andthe source regions 270 can be converted into dielectric materialportions by thermal conversion and/or plasma conversion of thesemiconductor materials into dielectric materials. For example, thermalconversion and/or plasma conversion can be employed to convert a surfaceportion of each epitaxial channel portion 11 into a dielectric spacer116, and to convert a surface portion of each source region 270 into asacrificial dielectric portion 616. In one embodiment, each dielectricspacer 116 can be topologically homeomorphic to a torus, i.e., generallyring-shaped. As used herein, an element is topologically homeomorphic toa torus if the shape of the element can be continuously stretchedwithout destroying a hole or forming a new hole into the shape of atorus. The dielectric spacers 116 include a dielectric material thatincludes the same semiconductor element as the epitaxial channelportions 11 and additionally includes at least one non-metallic elementsuch as oxygen and/or nitrogen such that the material of the dielectricspacers 116 is a dielectric material. In one embodiment, the dielectricspacers 116 can include a dielectric oxide, a dielectric nitride, or adielectric oxynitride of the semiconductor material of the epitaxialchannel portions 11. Likewise, each sacrificial dielectric portion 616includes a dielectric material that includes the same semiconductorelement as the source regions 270 and additionally includes at least onenon-metallic element such as oxygen and/or nitrogen such that thematerial of the sacrificial dielectric portions 616 is a dielectricmaterial. In one embodiment, the sacrificial dielectric portions 616 caninclude a dielectric oxide, a dielectric nitride, or a dielectricoxynitride of the semiconductor material of the source region 270.

Referring to FIG. 8, a backside blocking dielectric layer (not shown)can be optionally formed. The backside blocking dielectric layer, ifpresent, comprises a dielectric material that functions as a controlgate dielectric for the control gates to be subsequently formed in thebackside recesses 43. In case a blocking dielectric 502 is presentwithin each memory opening, the backside blocking dielectric layer isoptional. In case a blocking dielectric layer 502 is omitted, thebackside blocking dielectric layer is present.

At least one metallic material can be deposited in the plurality ofbackside recesses 43, on the sidewalls of the at least one the backsidecontact trench 79, and over the top surface of the second contact leveldielectric layer 73. As used herein, a metallic material refers to anelectrically conductive material that includes at least one metallicelement

The metallic material can be deposited by a conformal deposition method,which can be, for example, chemical vapor deposition (CVD), atomic layerdeposition (ALD), electroless plating, electroplating, or a combinationthereof. The metallic material can be an elemental metal, anintermetallic alloy of at least two elemental metals, a conductivenitride of at least one elemental metal, a conductive metal oxide, aconductive doped semiconductor material, a conductivemetal-semiconductor alloy such as a metal silicide, alloys thereof, andcombinations or stacks thereof. Non-limiting exemplary metallicmaterials that can be deposited in the plurality of backside recesses 43include tungsten, tungsten nitride, titanium, titanium nitride,tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment,the metallic material can comprise a metal such as tungsten and/or metalnitride. In one embodiment, the metallic material for filling theplurality of backside recesses 43 can be a combination of titaniumnitride layer and a tungsten fill material.

In one embodiment, the metallic material can be deposited by chemicalvapor deposition or atomic layer deposition. In one embodiment, themetallic material can be employing at least one fluorine-containingprecursor gas as a precursor gas during the deposition process. In oneembodiment, the molecule of the at least one fluorine-containingprecursor gas cam comprise a compound of at least one tungsten atom andat least one fluorine atom. For example, if the metallic materialincludes tungsten, WF6 and H2 can be employed during the depositionprocess.

A plurality of electrically conductive layers 46 can be formed in theplurality of backside recesses 43, and a contiguous metallic materiallayer 46L can be formed on the sidewalls of each backside contact trench79 and over the at least one contact level dielectric layer (71,73).Thus, each sacrificial material layer 42 can be replaced with anelectrically conductive layer 46. A backside cavity 79′ is present inthe portion of each backside contact trench 79 that is not filled withthe backside blocking dielectric layer 66 and the contiguous metallicmaterial layer 46L.

Referring to FIG. 9, the deposited metallic material of the contiguousmetallic material layer 46L is etched back from the sidewalls of eachbackside contact trench 79 and from above the second contact leveldielectric layer 73, for example, by an isotropic etch. Each remainingportion of the deposited metallic material in the backside recesses 43constitutes an electrically conductive layer 46. Each electricallyconductive layer 46 can be a conductive line structure. Thus, thesacrificial material layers 42 are replaced with the electricallyconductive layers 46.

Each electrically conductive layer 46 can function as a combination of aplurality of control gate electrodes located at a same level and a wordline electrically interconnecting, i.e., electrically shorting, theplurality of control gate electrodes located at the same level. Theplurality of control gate electrodes within each electrically conductivelayer 46 are the control gate electrodes for the vertical memory devicesincluding the memory stack structures 55. In other words, eachelectrically conductive layer 46 can be a word line that functions as acommon control gate electrode for the plurality of vertical memorydevices. Optionally, the sacrificial dielectric portions 616 can beremoved from above the source regions 270 during the last processingstep of the anisotropic etch.

Referring to FIG. 10, an insulating material layer can be formed in theat least one backside contact trench 79 and over the second contactlevel dielectric layer 73 by a conformal deposition process. Exemplaryconformal deposition processes include, but are not limited to, chemicalvapor deposition and atomic layer deposition. The insulating materiallayer includes an insulating material such as silicon oxide, siliconnitride, a dielectric metal oxide, an organosilicate glass, or acombination thereof. The thickness of the insulating material layer canbe in a range from 1.5 nm to 60 nm, although lesser and greaterthicknesses can also be employed.

Subsequently, an anisotropic etch is performed to remove horizontalportions of the insulating material layer and to optionally remove thehorizontal portion of the backside blocking dielectric layer 66 fromabove the second contact level dielectric layer 73. Each remainingportion of the insulating material layer inside a backside contacttrench 79 constitutes a vertically elongated annular structure with avertical cavity therethrough, which is herein referred to as aninsulating spacer 74. In one embodiment, an annular bottom surface ofthe insulating spacer 74 contacts a top surface of the source region270.

Each insulating spacer 74 can be formed over the sidewalls of thebackside contact trench 79, and can be formed directly on substantiallyvertical sidewalls of the backside blocking dielectric layer 66 anddirectly on the sidewalls of the electrically conductive layers 46,i.e., directly on the sidewalls of the metallic material portions 46.The thickness of each insulating spacer 74, as measured at a bottomportion thereof, can be in a range from 1.5 nm to 60 nm, although lesserand greater thicknesses can also be employed. In one embodiment, thethickness of the insulating spacer 74 can be in a range from 3 nm to 10nm. Each insulating spacer 74 laterally surrounds a backside cavity 79′.

Referring to FIGS. 11A-11E, a backside contact via structure 76 isformed in each backside cavity 79′ by deposition of at least oneconductive material, which can include a metallic liner (such as TiN,TaN, or WN) and a conductive fill material (such as W, Cu, Al, Co, Ru,or a combination thereof). Excess portions of the at least oneconductive material can be removed, for example, by chemical mechanicalplanarization (CMP).

Various additional contact via structures can be formed throughdielectric material layers/portions of the exemplary structure. Forexample, peripheral device contact via structures (8G, 8A) can be formedin the peripheral device region to provide electrical contact to variousnodes of the peripheral devices. The peripheral device contact viastructures (8G, 8A) can include, for example, at least one gate contactvia structure 8G and at least one active region contact via structure8A. In one embodiment, the memory contact via structures 88 may beformed during the same step as the peripheral device contact viastructures (8G, 8A). Likewise, word line contact via structures (notshown for clarity) may also be formed during the same processing stepsto contact the word lines.

Each field effect transistor (e.g., source select transistor) thatcontrols flow of electrical current through a memory stack structure 55includes a vertical channel composed of a semiconductor channel 60 andan optional epitaxial channel portion 11, and a horizontal channelportion that includes a portion of the doped pocket region 260 and mayinclude a portion of a doped well, which can be a portion of thesemiconductor material layer 10 located between the doped pocket region260 and a respective epitaxial channel portion 11. The mechanism forcontrolling the threshold voltages of field effect transistors includescontrol of electron mobility at, and near, the interface between thedoped pocket region 260 and the doped well.

Specifically, as shown in FIG. 11C, for a field effect transistorincluding an outer epitaxial channel portion 11O and an overlyingsemiconductor channel 60 of a first (outer) memory stack structure 55, ahigh threshold voltage region HVTR is formed around the interface 261between the doped pocket region 260 and the doped well (which can be aportion of the semiconductor material layer 10). The relatively highdopant concentration level of the first conductivity type dopants in thedoped pocket region 260 compared to the dopant concentration level inthe well in layer 10 induces formation of the high threshold voltageregion HVTR, in which the gate electric field generated by the gatevoltage applied to a source select gate electrode (as embodied as thelowest level electrically conductive layer 46) is weak. The weak gateelectric field forms a path of low charge carrier mobility in the highthreshold voltage region HVTR. For example, if the first conductivitytype is p-type, the high threshold voltage region HVTR provides a regionof low electron mobility.

In contrast, as shown in FIG. 11D, high mobility regions HMR are formedin the lower p-type dopant concentration well in layer 10 near a topportion of the interface 261 between the higher p-type dopantconcentration region 260 and portion 11. A high mobility region HMR canbe provided at the junction of the first interface 261 and a secondinterface 262. The second interface 262 is the interface between thedoped well in layer 10 and dielectric material layers (12, 31) thatfunction as a gate dielectric, and the first interface 261 is the sameinterface between the doped pocket region 260 and the doped well inlayer 10 described above. Due to low atomic concentration of the dopantsof the first conductivity type in the doped well in layer 10 compared toin region 260 and portion 11, charge carrier mobility is enhanced ineach high mobility region HMR, and the high mobility regions HMR becomesprimary paths for opposite conductivity type charge carrier conductionwithin the channels of the field effect transistors. For example, if thefirst conductivity type is p-type, the high mobility regions HMRprovides primary paths for electron conduction in the channels of thefield effect transistors.

Without wishing to be bound by a particular theory, it is believed thatby inducing an areal overlap between the doped pocket region 260 and theouter epitaxial channel portions 11O through the anneal process (whichforms the doped pocket region 260) while preventing an areal overlapbetween the doped pocket region 260 and the inner epitaxial channelportions 11I, the high threshold voltage regions HVTR are formed only incontact with the outer epitaxial channel portions 11O, and not incontact with the inner epitaxial channel portions 11I. Thus, theshortest charge carrier path a) illustrated in FIG. 11E is not a paththat provides majority of electrical current during the on-state for afield effect transistor including an outer epitaxial channel portion11O. In contrast, a predominant portion (i.e., majority) of chargecarriers injected from the source region 270 passes through the highmobility regions HMR even for a field effect transistor including anouter epitaxial channel portion 11O as indicated by a primary currentpath b) illustrated in FIG. 11E.

For a field effect transistor including an inner epitaxial channelportion 11I, a predominant portion of charge carriers passes through ahigh mobility region HMR. Therefore, the high mobility regions HMRdetermine the level of on-current for each field effect transistor forthe vertical memory devices including the memory stack structures 55.The threshold voltages for the field effect transistors are determinedby the dopant concentration profiles in the high mobility regions HMR.Correspondingly, the threshold voltages for the field effect transistorscan be the same irrespective of the locations of the memory stackstructures 55, and the threshold voltage differential between the first(outer) memory stack structures and the second (inner) memory stackstructures, which would be present in the absence of the doped pocketregion 260, can be eliminated or minimized. In other words, by formingthe doped pocket region 260 that partially overlaps the areas of onlythe outer but not inner stack structures, the same threshold voltagescan be provided for the field effect transistors of the outer memorystack structures and the inner memory stack structures, and thethreshold voltage differential between the outer memory stack structuresand the inner memory stack structures can be minimized or eliminated.

FIG. 12 illustrates a simulated current voltage plot illustrating adifference in the channel current through an outer device semiconductorchannel and an inner device semiconductor channel due to presence of adoped pocket region according to an embodiment of the presentdisclosure. The x-axis represents the gate bias voltage, which can bethe source-side select gate voltage V_(SGSB). The y-axis represents thechannel current as a function of the gate bias voltage. The graphillustrates the channel current for four n-type field effect transistorsemploying a p-doped well as a portion of a respective channel. A firstcurve 121 a represents the channel current for an outer field effecttransistor that does not employ a doped pocket region, i.e., aconventional field effect transistor including an outer epitaxialchannel portion and not employing the configuration of the embodimentsof the present disclosure. A second curve 121 b represents the channelcurrent for an inner field effect transistor that does not employ adoped pocket region, i.e., a conventional field effect transistorincluding an inner epitaxial channel portion and not employing theconfiguration of the embodiments of the present disclosure. A thirdcurve 131 a represents the channel current for an outer field effecttransistor of the present disclosure, i.e., a field effect transistorincluding an outer epitaxial channel portion 11O with pocket 260according to the embodiments of the present disclosure. A fourth curve131 b represents the channel current for an inner field effecttransistor of the present disclosure, i.e., a field effect transistorincluding an inner epitaxial channel portion 11I and pocket region 260according to the embodiments of the present disclosure. The channelcurrent I is plotted on a log scale. The threshold channel currentI_(th) that determines the threshold voltages of the field effecttransistors is shown as a horizontal line.

As described with respect to FIGS. 11C and 11D, even under the same gateselect electrode (as embodied as a bottommost electrically conductivelayer 46), different threshold voltage (V_(t)) regions are formed alongpath a) and path b) in FIG. 11E. A high threshold voltage region HVTR isformed at the corner part of each outer epitaxial channel portion 11O.HVTR has a higher threshold voltage than the horizontal portion of thechannel in the well in layer 10. In case the first conductivity type isp-type and the second conductivity type is n-type, electrons pass fromthe source region 270 to a respective semiconductor channel within thememory stack structures 55 through a horizontal channel portion betweenthe source region 270 and a respective epitaxial channel portion 11, andthrough a vertical portion which is an epitaxial channel portion 11. Theelectric field from the select gate electrode is weaker in the highthreshold voltage region HVTR located at the corner part of each outerepitaxial channel portion 11O than in other parts of the pocket region260, such as in the horizontal channel part in the pocket region 260.This is believed to be due to the lower density of electric force linesfrom the select gate in this corner region, due to the channel shape atthe corner.

Furthermore, it is believed that the electric field from the select gateelectrode is weaker in the high threshold voltage region HVTR located atthe corner part of each outer epitaxial channel portion 11O than theelectric field from the same select gate electrode at the corner part ofeach inner epitaxial channel portion 11I. The threshold voltage islikewise higher in HVTR than at the corner of the inner epitaxialchannel portions 11I. This is believed to occur because the corner partof each outer epitaxial channel portion 11O is located in the heavierdoped pocket region 260, while the corner part of each inner epitaxialchannel portion 11I is located in the lighter doped well in layer 10.

The threshold voltage of path a) is determined by the threshold voltageof the HVTR. Thus, the threshold voltage along path a) is higher thanalong path b) and the mobility of electrons along the path a) is lowerthan the mobility of electrons along the path b). Thus, electrons arebelieved to selectively follow the path b) rather than path a) to beinjected into the semiconductor channels in the memory stack structures55.

The effect of the increase in boron doping due to formation of a dopedpocket region 260 is schematically shown as shifts in the current curvesfrom the first curve 121 a to the third curve 131 a, and from the secondcurve 121 b to the fourth curve 131 b. The corresponding shifts in thethreshold voltage due to formation of a doped pocket region 260 are alsoshown, which include the shift from the threshold voltage for an outertransistor without a doped pocket region V_(th) _(_) _(a) _(_) _(NPKT)to the threshold voltage for an outer transistor with a doped pocketregion V_(th) _(_) _(a) _(_) _(PKT), and the shift from the thresholdvoltage for an inner transistor without a doped pocket region V_(th)_(_) _(b) _(_) _(NPKT) to the threshold voltage for an inner transistorwith a doped pocket region V_(th) _(_) _(b) _(_) _(PKT). In oneembodiment, the difference between outer and inner transistors with thepocket region (i.e., the difference between V_(th) _(_) _(a) _(_) _(PKT)and V_(th) _(_) _(b) _(_) _(PKT)) is less than the difference betweenouter and inner transistors without the pocket region (i.e., thedifference between V_(th) _(_) _(a) _(_) _(NPKT) and V_(th) _(_) _(b)_(_) _(NPKT)) can be reduced through use of the doped pocket region 260.

In one embodiment, the exemplary structure of the present disclosure caninclude a monolithic three-dimensional memory device. The monolithicthree-dimensional memory device can include a stack of alternatinglayers comprising insulating layers 32 and electrically conductivelayers 46 and located over a doped well (which can be a portion of thesemiconductor material layer 10 and/or the substrate semiconductor layer9) located in a substrate (9, 10) and having a doping of a firstconductivity type at a first dopant concentration level. A plurality ofmemory stack structures 55 extends through the stack of alternatinglayers. A first backside contact via structure 76 can extend through thestack and can be laterally spaced from the plurality of memory stackstructures 55. A source region 270 underlies the first backside contactvia structure 76, and has a doping of a second conductivity that is theopposite of the first conductivity type. A doped pocket region 260laterally surrounds the source region 270. The doped pocket region 260has a doping of the first conductivity type at a second dopantconcentration level that is higher than the first dopant concentrationlevel. An interface 261 between the doped pocket region 260 and thedoped well underlies at least one first memory stack structure (whichcan be outer memory stack structures) among the plurality of memorystack structures 55.

In one embodiment, each of the at least one first memory stack structurecontacts a top surface of a respective epitaxial channel portion 11Othat contacts the interface 261. In one embodiment, at least one secondmemory stack structure among the plurality of memory stack structures 55overlies the doped well in layer 10 and does not overlie the dopedpocket region 260. In one embodiment, a lateral distance between thesource region 270 and the doped well is uniform around a periphery ofthe source region 270. The uniform lateral distance is due to theuniform nature of the dopant diffusion that occurs during the anneal atan elevated temperature that is employed to form the doped pocket region260. In one embodiment, each of the plurality of memory stack structures55 comprises a semiconductor channel 60 of a respective verticaltransistor. The difference between a mean threshold voltage of the atleast one first memory stack structure (i.e., the outer memory stackstructures overlying the outer epitaxial channel portions 11O) and amean threshold voltage of the at least one second memory stack structure(i.e., the inner memory stack structures overlying the inner epitaxialchannel portions 11I) is not greater than 0.5 V. In one embodiment, thedifference between the mean threshold voltages of the first and secondmemory stack structures can be not greater than 0.3 V, such as 0 to 0.5V, for example 0.1 to 0.25V. Thus, a difference between a mean thresholdvoltage of the at least one first (outer) memory stack structure and amean threshold voltage of the at least one second (inner) memory stackstructure is not greater than 0.5 V during operation of the memorydevice, such as during read, write or erase operation of the NANDdevice.

In one embodiment, the first backside contact via structure 76 laterallyextends along a lengthwise direction, and the interface 261 between thedoped pocket region 260 and the doped well in layer 10 can laterallyextend along the same lengthwise direction. In one embodiment, asidewall of the source region 270 laterally extends along the lengthwisedirection, and the interface is laterally spaced from the sidewall ofthe source region 270 by a uniform lateral distance.

A second backside contact via structure 76 can extend through the stack.The plurality of memory stack structures 55 can be located between thefirst backside contact via structure 76 and the second backside contactvia structure 76. In one embodiment, the first conductivity type isp-type, the second conductivity type is n-type, the doped pocket region260 comprises boron as dopants of the first conductivity type, and thesource region 270 comprises arsenic or phosphorus and additionallycomprises boron at a concentration lower than the atomic concentrationof arsenic and phosphorus. In one embodiment, the atomic concentrationof dopants of the first conductivity type (such as boron concentration)in the source region 270 can be greater than the atomic concentration ofdopants of the first conductivity type (such as boron concentration) inthe doped pocket region 260.

In one embodiment, each memory stack structure 55 can include, fromoutside to inside, at least one blocking dielectric (501, 503), a memorymaterial layer 504, a tunneling dielectric 506, and a semiconductorchannel 60 contacting an overlying drain region 63.

In one embodiment, the memory device of the present disclosure can be amonolithic three-dimensional memory device comprising a vertical NANDdevice located over the substrate (9, 10), and the electricallyconductive layers 46 can comprise, or are electrically connected to, arespective word line of the vertical NAND device. The substrate (9, 10)can comprise a silicon substrate. The vertical NAND device can comprisean array of monolithic three-dimensional NAND strings located over thesilicon substrate. At least one memory cell in a first device level ofthe three-dimensional array of NAND strings is located over anothermemory cell in a second device level of the three-dimensional array ofNAND string. The silicon substrate can contain an integrated circuitcomprising a driver circuit for the memory device located thereon.

The array of monolithic three-dimensional NAND strings can comprise aplurality of semiconductor channels. At least one end portion of each ofthe plurality of semiconductor channels extends substantiallyperpendicular to a top surface of the substrate (9, 10). In oneembodiment, the plurality of semiconductor channels can comprisehorizontal semiconductor channel portions that include a doped well(which is a portion of the semiconductor material layer 10) and thedoped pocket region 260 located between a source region 270 and theinner and outer epitaxial channel portions (11I, 11O), and the verticalsemiconductor channels 60 that are portions of the memory stackstructures 55. The array of monolithic three-dimensional NAND stringscan comprise a plurality of charge storage elements (which can beembodied as sections of a memory material layer 504 that is presentwithin each memory stack structure 55). Each charge storage element canbe located adjacent to a respective one of the plurality ofsemiconductor channels, i.e., adjacent to a respective verticalsemiconductor channel 60. The array of monolithic three-dimensional NANDstrings can comprise a plurality of control gate electrodes having astrip shape extending substantially parallel to the top surface of thesubstrate (9, 10). The plurality of control gate electrodes comprise atleast a first control gate electrode located in the first device leveland a second control gate electrode located in the second device level.

Although the foregoing refers to particular preferred embodiments, itwill be understood that the disclosure is not so limited. It will occurto those of ordinary skill in the art that various modifications may bemade to the disclosed embodiments and that such modifications areintended to be within the scope of the disclosure. Where an embodimentemploying a particular structure and/or configuration is illustrated inthe present disclosure, it is understood that the present disclosure maybe practiced with any other compatible structures and/or configurationsthat are functionally equivalent provided that such substitutions arenot explicitly forbidden or otherwise known to be impossible to one ofordinary skill in the art. All of the publications, patent applicationsand patents cited herein are incorporated herein by reference in theirentirety.

What is claimed is:
 1. A monolithic three-dimensional memory devicecomprising: a stack of alternating layers comprising insulating layersand electrically conductive layers and located over a semiconductorregion having a doping of a first conductivity type at a first dopantconcentration level; a plurality of memory stack structures extendingthrough the stack; a first backside contact via structure extendingthrough the stack and laterally spaced from the plurality of memorystack structures; a source region underlying the first backside contactvia structure and having a doping of a second conductivity that is theopposite of the first conductivity type; and a doped pocket regionlaterally surrounding the source region, having a doping of the firstconductivity type at a second dopant concentration level that is higherthan the first dopant concentration level, wherein an interface betweenthe doped pocket region and the semiconductor region underlies at leastone first memory stack structure among the plurality of memory stackstructures.
 2. The monolithic three-dimensional memory device of claim1, wherein: the semiconductor region comprises a doped well located inor over a substrate; and at least one second memory stack structureamong the plurality of memory stack structures overlies the doped welland does not overlie the doped pocket region.
 3. The monolithicthree-dimensional memory device of claim 2, wherein each of the at leastone first memory stack structure contacts a top surface of a respectiveepitaxial channel portion that contacts the interface.
 4. The monolithicthree-dimensional memory device of claim 2, wherein a lateral distancebetween the source region and the doped well is uniform around aperiphery of the source region.
 5. The monolithic three-dimensionalmemory device of claim 2, wherein: each of the plurality of memory stackstructures comprises a semiconductor channel of a respective verticaltransistor; and a difference between a mean threshold voltage of the atleast one first memory stack structure and a mean threshold voltage ofthe at least one second memory stack structure is not greater than 0.5V.
 6. The monolithic three-dimensional memory device of claim 2,wherein: the at least one first memory stack structure comprises a outerrow of first memory stack structures; and the at least one second memorystack structure comprises an inner row of first memory stack structureswhich is located farther from the first backside contact via structurethan the outer row.
 7. The monolithic three-dimensional memory device ofclaim 1, wherein: the first backside contact via structure laterallyextends along a lengthwise direction; the interface laterally extendsalong the lengthwise direction; a sidewall of the source regionlaterally extends along the lengthwise direction; and the interface islaterally spaced from the sidewall of the source region by a uniformlateral distance.
 8. The monolithic three-dimensional memory device ofclaim 1, further comprising a second backside contact via structureextending through the stack, wherein the plurality of memory stackstructures are located between the first backside contact via structureand the second backside contact via structure.
 9. The monolithicthree-dimensional memory device of claim 1, wherein: the firstconductivity type is p-type; the second conductivity type is n-type; thedoped pocket region comprises boron as dopants of the first conductivitytype; and the source region comprises arsenic or phosphorus as dopantsof the second conductivity type.
 10. The monolithic three-dimensionalmemory device of claim 2, wherein each memory stack structure comprises,from outside to inside: at least one blocking dielectric, a memorymaterial layer, a tunneling dielectric, and a semiconductor channelcontacting an overlying drain region.
 11. The monolithicthree-dimensional memory device of claim 10, wherein: the monolithicthree-dimensional memory device comprises a vertical NAND device locatedover the substrate; the electrically conductive layers comprise, or areelectrically connected to, a respective word line of the vertical NANDdevice; the substrate comprises a silicon substrate; the vertical NANDdevice comprises an array of monolithic three-dimensional NAND stringsover the silicon substrate; at least one memory cell in a first devicelevel of the array of monolithic three-dimensional NAND strings islocated over another memory cell in a second device level of the arrayof monolithic three-dimensional NAND strings; the silicon substratecontains an integrated circuit comprising a driver circuit for thememory device located thereon; and the array of monolithicthree-dimensional NAND strings comprises: a plurality of semiconductorchannels, wherein at least one end portion of each of the plurality ofsemiconductor channels extends substantially perpendicular to a topsurface of the substrate; a plurality of charge storage elements, eachcharge storage element located adjacent to a respective one of theplurality of semiconductor channels; and a plurality of control gateelectrodes having a strip shape extending substantially parallel to thetop surface of the substrate, the plurality of control gate electrodescomprise at least a first control gate electrode located in the firstdevice level and a second control gate electrode located in the seconddevice level.
 12. A method of manufacturing a memory device, comprising:forming a stack of alternating layers comprising insulating layers andspacer material layers over a substrate; forming a plurality of memorystack structures through the stack; forming a backside contact trenchextending through the stack and to the substrate; forming an implantedregion in a portion of the substrate underlying the backside contacttrench by implanting first conductivity type dopants and secondconductivity type dopants through the backside contact trench; andsimultaneously outdiffusing the first and the second conductivity typedopants employing an anneal process performed at an elevatedtemperature.
 13. The method of claim 12, wherein: dopants of a firstconductivity type diffuse farther than dopants of a second conductivitytype to form a doped pocket region having a doping of the firstconductivity type; and a source region having a doping of the secondconductivity type is formed underneath the backside contact trench. 14.The method of claim 13, wherein: the memory stack structures are formedover a doped well in the substrate, the doped well having a doping ofthe first conductivity type at a first dopant concentration level; thedoped pocket has a doping of the first conductivity type at a seconddopant concentration level that is higher than the first dopantconcentration level; an interface between the doped pocket region andthe doped well underlies at least one first memory stack structure amongthe plurality of memory stack structures; and the doped pocket regiondoes not underlie at least one second memory stack structure among theplurality of memory stack structures.
 15. The method of claim 14,wherein: each of the plurality of memory stack structures comprises asemiconductor channel of a respective vertical transistor; and processconditions of the anneal process are selected such that a differencebetween a mean threshold voltage of the at least one first memory stackstructure and a mean threshold voltage of the at least one second memorystack structure is not greater than 0.5 V.
 16. The method of claim 14,wherein: the at least one first memory stack structure comprises a outerrow of first memory stack structures; and the at least one second memorystack structure comprises an inner row of first memory stack structureswhich is located farther from the backside contact trench than the outerrow.
 17. The method of claim 13, further comprising: forming a backsidecontact via structure within the backside contact trench; forming memoryopenings extending through the stack of alternating layers and to thesubstrate; and forming an epitaxial channel portion in each memoryopening, wherein: the memory stack structures are formed on a respectiveepitaxial channel portion; and the doped pocket region laterallysurrounds the source region.
 18. The method of claim 13, wherein: thefirst conductivity type is p-type; the second conductivity type isn-type; the doped pocket region comprises boron as dopants of the firstconductivity type; and the source region comprises arsenic or phosphorusas dopants of the second conductivity type.
 19. The method of claim 12,wherein each memory stack structure comprises, from outside to inside:at least one blocking dielectric, a memory material layer, a tunnelingdielectric, and a semiconductor channel contacting an overlying drainregion.
 20. The method of claim 19, wherein: the monolithicthree-dimensional memory device comprises a vertical NAND device locatedover the substrate; the spacer material layers are formed aselectrically conductive layers or are replaced with electricallyconductive layers; the electrically conductive layers comprise, or areelectrically connected to, a respective word line of the vertical NANDdevice; the substrate comprises a silicon substrate; the vertical NANDdevice comprises an array of monolithic three-dimensional NAND stringsover the silicon substrate; at least one memory cell in a first devicelevel of the array of monolithic three-dimensional NAND strings islocated over another memory cell in a second device level of the arrayof monolithic three-dimensional NAND strings; the silicon substratecontains an integrated circuit comprising a driver circuit for thememory device located thereon; and the array of monolithicthree-dimensional NAND strings comprises: a plurality of semiconductorchannels, wherein at least one end portion of each of the plurality ofsemiconductor channels extends substantially perpendicular to a topsurface of the substrate; a plurality of charge storage elements, eachcharge storage element located adjacent to a respective one of theplurality of semiconductor channels; and a plurality of control gateelectrodes having a strip shape extending substantially parallel to thetop surface of the substrate, the plurality of control gate electrodescomprise at least a first control gate electrode located in the firstdevice level and a second control gate electrode located in the seconddevice level.
 21. A method of operating the monolithic three-dimensionalmemory device of claim 2, wherein a difference between a mean thresholdvoltage of the at least one first memory stack structure and a meanthreshold voltage of the at least one second memory stack structure isnot greater than 0.5 V during operation of the device.